Abstract

Register windowing has become a common sight in high speed processors, reducing the memory traffic required to preserve register contents over sub-routine invocations. However, approaches to register windowing have changed little since their introduction. In this article, the current windowing schemes (namely fixed-sized and variable-sized) are presented, along with methods of implementation. A number of disadvantages with these systems are identified, and the requirements for an improved register windowing mechanism defined. A new register windowing paradigm is presented, known as Shifting Register Windows , which is design to meet these requirements. This windowing system is first given in overview, followed by a more detailed description of the underlying model. Finally, a performance analysis of the model is presented, and conclusions drawn on speed and efficiency.