Modern civil engineers have big problems on their hands; more cars use our road networks every year, leading to ever increasing congestion. Knowing how to change a road network to relieve congestion without spending millions of pounds doing so is a tricky business. Traffic simulators can go some way to helping the engineers know how flows will alter with changes in the network. Such changes could be a new road, or even a simple modification to a signalized junction\'s phasing. Unfortunately, accurate simulators typically available to engineers are slow to execute, especially if the network being simulated is the size of a city. Real-time simulations are available, running on parallel platforms, but these are costly. This paper discusses the initial research into traffic simulation on programmable logic devices (PLDs). This promises simulations speeds which are faster than real time, but at a fraction of the cost of simulators based on parallel architecture. Rather that trying to map road networks directly onto the PLDs, we have used a hardware description language, XCircal, to model our hardware components. Each component corresponds to a part of a road network, such as a section of road or a one-lane to two-lane splitter. Using XCircal, full junctions can be modelled without touching the hardware. Results of a simulation are included, and these demonstrate that basic junction behaviour can be replicated in hardware.